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Compilation and architecture support for customized vector instruction extension., , , , , , , and . ASP-DAC, page 652-657. IEEE, (2012)Static and dynamic co-optimizations for blocks mapping in hybrid caches., , , , , and . ISLPED, page 237-242. ACM, (2012)CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters., , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 415-426. Springer, (2012)Towards layout-friendly high-level synthesis., , , and . ISPD, page 165-172. ACM, (2012)Generating Configurable Hardware from Parallel Patterns., , , , , , and . ASPLOS, page 651-665. ACM, (2016)Efficient Multiway Hash Join on Reconfigurable Hardware., , , , and . CoRR, (2019)Scalable interconnects for reconfigurable spatial architectures., , , , , and . ISCA, page 615-628. ACM, (2019)Plasticine: A Reconfigurable Architecture For Parallel Paterns., , , , , , , , and . ISCA, page 389-402. ACM, (2017)Automatic Generation of Efficient Accelerators for Reconfigurable Hardware., , , , , and . ISCA, page 115-127. IEEE Computer Society, (2016)Generating Configurable Hardware from Parallel Patterns., , , , , , and . CoRR, (2015)