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A Fully Pipelined and Dynamically Composable Architecture of CGRA.

, , , , and . FCCM, page 9-16. IEEE Computer Society, (2014)

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Accelerator-rich CMPs: From concept to real hardware., , , , , , and . ICCD, page 169-176. IEEE Computer Society, (2013)Optimization of interconnects between accelerators and shared memories in dark silicon., and . ICCAD, page 630-637. IEEE, (2013)ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures., , and . ISPASS, page 157-158. IEEE Computer Society, (2015)FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only)., and . FPGA, page 268. ACM, (2012)CMOST: a system-level FPGA compilation framework., , , , and . DAC, page 158:1-158:6. ACM, (2015)Domain-specific processor with 3D integration for medical image processing., , , , , and . ASAP, page 247-250. IEEE Computer Society, (2011)Energy-efficient computing using adaptive table lookup based on nonvolatile memories., , , , and . ISLPED, page 280-285. IEEE, (2013)A Fully Pipelined and Dynamically Composable Architecture of CGRA., , , , and . FCCM, page 9-16. IEEE Computer Society, (2014)Minimizing Computation in Convolutional Neural Networks., and . ICANN, volume 8681 of Lecture Notes in Computer Science, page 281-290. Springer, (2014)An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers., , , and . DAC, page 77:1-77:6. ACM, (2014)