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Synthesis Algorithm for Application-Specific Homogeneous Processor Networks., , , and . IEEE Trans. VLSI Syst., 17 (9): 1318-1329 (2009)LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization., , , and . IEEE Trans. VLSI Syst., 18 (4): 564-577 (2010)LUT-based FPGA technology mapping under arbitrary net-delay models., , , and . Computers & Graphics, 18 (4): 507-516 (1994)A Fully Pipelined and Dynamically Composable Architecture of CGRA., , , , and . FCCM, page 9-16. IEEE Computer Society, (2014)Energy-efficient computing using adaptive table lookup based on nonvolatile memories., , , , and . ISLPED, page 280-285. IEEE, (2013)Domain-specific processor with 3D integration for medical image processing., , , , , and . ASAP, page 247-250. IEEE Computer Society, (2011)Buffer block planning for interconnect planning and prediction., , and . IEEE Trans. VLSI Syst., 9 (6): 929-937 (2001)Pin assignment with global routing for general cell designs.. IEEE Trans. on CAD of Integrated Circuits and Systems, 10 (11): 1401-1412 (1991)Wire width planning for interconnect performance optimization., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (3): 319-329 (2002)Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (1): 24-39 (1998)