Author of the publication

Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique.

, , , , , and . ISVLSI, page 462-463. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Cooperative communication based barrier synchronization in on-chip mesh architectures., , , , and . IEICE Electronic Express, 8 (22): 1856-1862 (2011)Cooperative communication for efficient and scalable all-to-all barrier synchronization on mesh-based many-core NoCs., , , , , and . IEICE Electronic Express, 11 (18): 20140542 (2014)Special issue on networks on chip., , and . Journal of Systems Architecture, 50 (2-3): 61-63 (2004)Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips., , , , , , , and . JSW, 10 (2): 142-161 (2015)Modeling Communication with Synchronized Environments., and . Fundam. Inform., 86 (3): 343-369 (2008)A survey of memory architecture for 3D chip multi-processors., , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (5): 415-430 (2014)Rescuing healthy cores against disabled routers., , , , and . DFT, page 98-103. IEEE Computer Society, (2014)Scalability of network-on-chip communication architecture for 3-D meshes., , , , , , and . NOCS, page 114-123. IEEE Computer Society, (2009)Modelling Environment for Heterogeneous Systems based on MoCs., , , and . FDL, page 291-303. ECSI, (2005)A High Level Power Model for the Nostrum NoC., and . DSD, page 673-676. IEEE Computer Society, (2006)