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A survey of memory architecture for 3D chip multi-processors.

, , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (5): 415-430 (2014)

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Performance and power consumption analysis of memory efficient 3D network-on-chip architecture., , , , and . ICCA, page 340-344. IEEE, (2013)An RBF neural network-based dynamic virtual network embedding algorithm., , , and . Concurrency and Computation: Practice and Experience, (2019)A scalable distributed memory architecture for Network on Chip., , , , , and . APCCAS, page 1260-1263. IEEE, (2008)Mass message transmission aware buffer-less packet-circuit switching router for 3D NoC., , , , and . ICCA, page 983-986. IEEE, (2013)Exploring stacked main memory architecture for 3D GPGPUs., , , , , , and . ASICON, page 1-4. IEEE, (2015)Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links., , , , , and . ASICON, page 1-4. IEEE, (2015)An Analysis Method for Subliminal Affective Priming Effect Based on CEEMDAN and MPE., , , and . ChineseCSCW, volume 1042 of Communications in Computer and Information Science, page 323-334. Springer, (2019)A survey of memory architecture for 3D chip multi-processors., , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 38 (5): 415-430 (2014)Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips., , , , , and . ISCAS, page 1961-1964. IEEE, (2014)A Multidomain Survivable Virtual Network Mapping Algorithm., , and . Security and Communication Networks, (2017)