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Design of Fault-Tolerant and Reliable Networks-on-Chip., , , , and . ISVLSI, page 545-550. IEEE Computer Society, (2015)Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system., , , , and . Integration, (2019)Minimizing the system impact of router faults by means of reconfiguration and adaptive routing., , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, (2017)Online Path-Based Test Method for Network-on-Chip., , , , and . ISCAS, page 1-5. IEEE, (2019)Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip., , , and . ISCAS, page 1-5. IEEE, (2018)Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip., , , , , and . ISCAS, page 1-4. IEEE, (2017)Rescuing healthy cores against disabled routers., , , , and . DFT, page 98-103. IEEE Computer Society, (2014)WeNA: Deterministic Run-time Task Mapping for Performance Improvement in Many-core Embedded Systems., , , , and . Embedded Systems Letters, 7 (4): 93-96 (2015)Optimizing the location of ECC protection in network-on-chip., , , , and . CODES+ISSS, page 19:1-19:10. ACM, (2016)A low latency fault tolerant transmission mechanism for Network-on-Chip., , , and . ISCAS, page 1-4. IEEE, (2017)