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Cooperative communication based barrier synchronization in on-chip mesh architectures.

X. Chen, Z. Lu, A. Jantsch, S. Chen, and H. Liu. IEICE Electronic Express, 8 (22): 1856-1862 (2011)

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Jingshan Chen University of Stuttgart

Optimization-based trajectory planning for transport collaboration of heterogeneous systemsJ. Chen, W. Luo, H. Ebel, and P. Eberhard. Automatisierungstechnik, 72 (2): 80-90 (2024)

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

The Impact of Unsteadiness on the Aerodynamic Loads of a Floating Offshore Wind TurbineC. Schulz, U. Özinan, S. Netzband, P. Cheng, and M. Abdel-Maksoud. EERA Deepwind Conference 2023, 2626, page 012064. Institute of Physics, (2023)Lidar-based virtual load sensors for mooring lines using artificial neural networksM. Gräfe, U. Özinan, and P. Cheng. EERA Deepwind Conference 2023, 2626, page 012036. Institute of Physics, (2023)Impact of probe volume and peak detection methods on lidar rotor effective wind speed and turbulence intensity estimationsF. Costa, A. Peña, V. Pettas, and P. Cheng. EERA Deepwind Conference 2023, 2626, page 012020. Institute of Physics, (2023)

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Other publications of authors with the same name

FT-Matrix: A Coordination-Aware Architecture for Signal Processing.S. Chen, Y. Wang, S. Liu, J. Wan, H. Chen, H. Liu, K. Zhang, X. Liu, and X. Ning. IEEE Micro, 34 (6): 64-73 (2014)A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition.X. Chen, Y. Lei, Z. Lu, and S. Chen. IEEE Trans. VLSI Syst., 26 (10): 1953-1966 (2018)An Efficient Parallel Algorithm for H.264/AVC Encoder.S. Sun, and S. Chen. PDCAT, page 66-69. IEEE Computer Society, (2008)Handling shared variable synchronization in multi-core Network-on-Chips with distributed memory.X. Chen, Z. Lu, A. Jantsch, and S. Chen. SoCC, page 467-472. IEEE, (2010)Efficient bit-rate estimation technique for CABAC.S. Chen, and S. Sun. APCCAS, page 514-517. IEEE, (2008)Performance Analysis of Homogeneous On-Chip Large-Scale Parallel Computing Architectures for Data-Parallel Applications.X. Chen, Z. Lu, A. Jantsch, S. Chen, Y. Guo, S. Chen, and H. Chen. J. Electrical and Computer Engineering, (2015)Architecture Design Trade-offs among VLIW SIMD and Multi-core Schemes.Y. Wang, S. Chen, K. Zhang, H. Chen, and X. Chen. IPDPS Workshops, page 1649-1658. IEEE Computer Society, (2012)Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform.S. Chen, S. Chen, H. Gu, H. Chen, Y. Yin, X. Chen, S. Sun, S. Liu, and Y. Wang. HPCC, page 465-470. IEEE, (2010)Architectural Implications for SIMD Processors in the Wireless Communication Domain.Y. Wang, K. Zhang, J. Wan, S. Liu, X. Ning, and S. Chen. HPCC-ICESS, page 1199-1204. IEEE Computer Society, (2012)Implementation of a dynamic wordlength SIMD multiplier.Y. Liu, L. Liu, V. Öwall, and S. Chen. NORCHIP, page 1-4. IEEE, (2014)

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Disambiguation of "Chen, Shuming"

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Cooperative communication based barrier synchronization in on-chip mesh architectures.

Please choose a person to relate this publication to

Jingshan Chen University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Chen, Shuming"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Cooperative communication based barrier synchronization in on-chip mesh architectures.

Please choose a person to relate this publication to

Jingshan Chen University of Stuttgart

Univ. -Prof. Dr. Po Wen Cheng University of Stuttgart

Hong Chen University of Stuttgart

Yiyin Chen University of Stuttgart

Jun Chen University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Cooperative communication based barrier synchronization in on-chip mesh architectures.