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A shorted global clock design for multi-GHz 3D stacked chips., , , , , and . VLSIC, page 170-171. IEEE, (2012)Numerical modeling of advanced semiconductor devices., , , , , , , , , and . IBM Journal of Research and Development, 36 (2): 208-232 (1992)Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip., , , , , , , , , and 1 other author(s). ICCD, page 279-285. IEEE Computer Society, (1997)Wafer-level 3D integration technology., , , , , , , , , and . IBM Journal of Research and Development, 52 (6): 583-597 (2008)A half-micron CMOS logic generation., , , , , , , , , and 14 other author(s). IBM Journal of Research and Development, 39 (1-2): 215-228 (1995)Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 373-384 (2016)Thermal analysis of multi-layer functional 3D logic stacks., , , , , , , , and . 3DIC, page 1-4. IEEE, (2016)