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IBM POWER6 microprocessor physical design and design methodology., , , , , , , , , and 9 other author(s). IBM Journal of Research and Development, 51 (6): 685-714 (2007)A Resonant Global Clock Distribution for the Cell Broadband Engine Processor., , , , , , , , , and . J. Solid-State Circuits, 44 (1): 64-72 (2009)Design of Resonant Global Clock Distributions., , and . ICCD, page 248-253. IEEE Computer Society, (2003)New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems., and . ASYNC, IEEE Computer Society, (2005)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)On-chip Timing Uncertainty Measurements on IBM Microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor., , , , and . ISSCC, page 298-604. IEEE, (2007)Full-wave PEEC time-domain method for the modeling of on-chipinterconnects., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (7): 877-886 (2001)Subtractive Router for Tree-Driven-Grid Clocks., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 31 (6): 868-877 (2012)The circuit and physical design of the POWER4 microprocessor., , , , , , , , and . IBM J. Res. Dev., 46 (1): 27-52 (2002)