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On-chip Timing Uncertainty Measurements on IBM Microprocessors.

R. Franch, P. Restle, J. Norman, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K. van Goor, and G. Salem. ITC, page 1-7. IEEE Computer Society, (2008)

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A Resonant Global Clock Distribution for the Cell Broadband-Engine Processor.S. Chan, P. Restle, T. Bucelot, S. Weitzel, J. Keaty, J. Liberty, B. Flachs, R. Volant, P. Kapusta, and J. Zimmerman. ISSCC, page 512-513. IEEE, (2008)Cell Processor Low-Power Design Methodology.D. Stasiak, R. Chaudhry, D. Cox, S. Posluszny, J. Warnock, S. Weitzel, D. Wendel, and M. Wang. IEEE Micro, 25 (6): 71-78 (2005)On-chip timing uncertainty measurements on IBM microprocessors.R. Franch, P. Restle, J. Norman, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K. van Goor, and G. Salem. ITC, page 1-7. IEEE Computer Society, (2007)Implementation of the 65nm Cell Broadband Engine.M. Riley, B. Flachs, S. Dhong, G. Gervais, S. Weitzel, M. Wang, D. Boerstler, M. Bolliger, J. Keaty, J. Pille and 4 other author(s). CICC, page 717-720. IEEE, (2007)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system.J. Warnock, Y. Chan, W. Huott, S. Carey, M. Fee, H. Wen, M. Saccamango, F. Malgioglio, P. Meaney, D. Plass and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.D. Pham, H. Anderson, E. Behnen, M. Bolliger, S. Gupta, H. Hofstee, P. Harvey, C. Johns, J. Kahle, A. Kameyama and 13 other author(s). ASP-DAC, page 871-878. IEEE, (2006)On-chip Timing Uncertainty Measurements on IBM Microprocessors.R. Franch, P. Restle, J. Norman, W. Huott, J. Friedrich, R. Dixon, S. Weitzel, K. van Goor, and G. Salem. ITC, page 1-7. IEEE Computer Society, (2008)The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor.D. Wendel, R. Kalla, R. Cargnoni, J. Clabes, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, W. Starke, S. Taylor and 4 other author(s). ISSCC, page 102-103. IEEE, (2010)The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.D. Pham, E. Behnen, M. Bolliger, H. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, B. Le, Y. Masubuchi and 8 other author(s). CICC, page 45-49. IEEE, (2005)

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On-chip Timing Uncertainty Measurements on IBM Microprocessors.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML On-chip Timing Uncertainty Measurements on IBM Microprocessors.

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On-chip Timing Uncertainty Measurements on IBM Microprocessors.