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%0 Conference Paper
%1 conf/vlsic/PangRWSFM12
%A Pang, Liang-Teck
%A Restle, Phillip J.
%A Wordeman, Matthew R.
%A Silberman, Joel A.
%A Franch, Robert L.
%A Maier, Gary W.
%B VLSIC
%D 2012
%I IEEE
%K dblp
%P 170-171
%T A shorted global clock design for multi-GHz 3D stacked chips.
%U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#PangRWSFM12
%@ 978-1-4673-0848-9
@inproceedings{conf/vlsic/PangRWSFM12,
added-at = {2016-03-16T00:00:00.000+0100},
author = {Pang, Liang-Teck and Restle, Phillip J. and Wordeman, Matthew R. and Silberman, Joel A. and Franch, Robert L. and Maier, Gary W.},
biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2c447c03275edf4f98793f7eb35a646c6/dblp},
booktitle = {VLSIC},
crossref = {conf/vlsic/2012},
ee = {http://dx.doi.org/10.1109/VLSIC.2012.6243844},
interhash = {2489c3bfa66654419d740317b193fa3c},
intrahash = {c447c03275edf4f98793f7eb35a646c6},
isbn = {978-1-4673-0848-9},
keywords = {dblp},
pages = {170-171},
publisher = {IEEE},
timestamp = {2016-03-17T10:33:16.000+0100},
title = {A shorted global clock design for multi-GHz 3D stacked chips.},
url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2012.html#PangRWSFM12},
year = 2012
}
