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IC laser trimming speed-up through wafer-level spatial correlation modeling.

, , , , , , and . ITC, page 1-7. IEEE Computer Society, (2014)

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Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications., , and . IEEE Trans. Computers, 60 (4): 450-451 (2011)On the identification of modular test requirements for low cost hierarchical test path construction., and . Integration, 40 (3): 315-325 (2007)Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain., , , , , and . Proceedings of the IEEE, 102 (8): 1207-1228 (2014)Guest Editorial Special Section on Hardware Security and Trust., , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (6): 873-874 (2015)Nonlinear decision boundaries for testing analog circuits., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 24 (11): 1760-1773 (2005)Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors.. DFT, page 421-421. IEEE Computer Society, (2009)VeriCoq: A Verilog-to-Coq converter for proof-carrying hardware automation., and . ISCAS, page 29-32. IEEE, (2015)Spatial estimation of wafer measurement parameters using Gaussian process models., , , and . ITC, page 1-8. IEEE Computer Society, (2012)Integrated optimization of semiconductor manufacturing: A machine learning approach., and . ITC, page 1-10. IEEE Computer Society, (2012)Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case., , and . ICCD, page 194-197. IEEE Computer Society, (2003)