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Efficient Pattern Mapping for Deterministic Logic BIST.

V. Gherman, H. Wunderlich, H. Vranken, F. Hapke, M. Wittke, and M. Garbers. ITC, page 48-56. IEEE Computer Society, (2004)

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Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Deterministic logic BIST for transition fault testing.V. Gherman, H. Wunderlich, J. Schlöffel, and M. Garbers. IET Computers & Digital Techniques, 1 (3): 180-186 (2007)Efficient Pattern Mapping for Deterministic Logic BIST.V. Gherman, H. Wunderlich, H. Vranken, F. Hapke, M. Wittke, and M. Garbers. ITC, page 48-56. IEEE Computer Society, (2004)Error-correction schemes with erasure information for fast memories.S. Evain, and V. Gherman. ETS, page 1-6. IEEE Computer Society, (2013)Implementing a Scheme for External Deterministic Self-Test.A. Hakmi, H. Wunderlich, V. Gherman, M. Garbers, and J. Schlöffel. VTS, page 101-106. IEEE Computer Society, (2005)Generalized parity-check matrices for SEC-DED codes with fixed parity.V. Gherman, S. Evain, N. Seymour, and Y. Bonhomme. IOLTS, page 198-201. IEEE Computer Society, (2011)Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths.S. Sarrazin, S. Evain, I. Panades, L. de Barros Naviner, and V. Gherman. IOLTS, page 160-163. IEEE, (2014)Is aproximate computing suitable for selective hardening of arithmetic circuits?B. Deveautour, A. Virazel, P. Girard, S. Pravossoudovitch, and V. Gherman. DTIS, page 1-6. IEEE, (2018)Error prediction based on concurrent self-test and reduced slack time.V. Gherman, J. Massas, S. Evain, S. Chevobbe, and Y. Bonhomme. DATE, page 1626-1631. IEEE, (2011)System-level hardware-based protection of memories against soft-errors.V. Gherman, S. Evain, M. Cartron, N. Seymour, and Y. Bonhomme. DATE, page 1222-1225. IEEE, (2009)Shadow-scan design with low latency overhead and in-situ slack-time monitoring.S. Sarrazin, S. Evain, I. Panades, A. Valentian, S. Pajaniradja, L. de Barros Naviner, and V. Gherman. ETS, page 1-6. IEEE, (2014)

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Disambiguation of "Gherman, Valentin"

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Efficient Pattern Mapping for Deterministic Logic BIST.

Please choose a person to relate this publication to

Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Gherman, Valentin"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Efficient Pattern Mapping for Deterministic Logic BIST.

Please choose a person to relate this publication to

Valentin Leipe University of Stuttgart

Valentin Kamm University of Stuttgart

Valentin Wagner University of Stuttgart

Valentin Bayer University of Stuttgart

Valentin Honold University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Efficient Pattern Mapping for Deterministic Logic BIST.