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Cell-aware experiences in a high-quality automotive test suite., , , , , , , , , and 5 other author(s). ETS, page 1-6. IEEE, (2014)PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits., , , , , and . ISVLSI, page 212-217. IEEE Computer Society, (2005)Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects., , , , and . ITC, page 1-10. IEEE Computer Society, (2007)X-masking during logic BIST and its impact on defect coverage., , , , , , , and . IEEE Trans. VLSI Syst., 14 (2): 193-202 (2006)Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults., , , , , and . MEMOCODE, page 181-187. IEEE Computer Society, (2007)Efficient Pattern Mapping for Deterministic Logic BIST., , , , , and . ITC, page 48-56. IEEE Computer Society, (2004)X-Masking During Logic BIST and Its Impact on Defect Coverage., , , , , , , and . ITC, page 442-451. IEEE Computer Society, (2004)ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume., , , , and . ITC, page 1069-1078. IEEE Computer Society, (2003)Fault collapsing of multi-conditional faults., , and . DDECS, page 42-47. IEEE Computer Society, (2013)A new SAT-based ATPG for generating highly compacted test sets., , , , and . DDECS, page 230-235. IEEE, (2012)