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Cell-aware analysis for small-delay effects and production test results from different fault models., , , , , , , and . ITC, page 1-8. IEEE Computer Society, (2011)Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation)., , , , and . it - Information Technology, 51 (2): 102-111 (2009)PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits., , , , , and . ISVLSI, page 212-217. IEEE Computer Society, (2005)Deterministic Logic BIST for Transition Fault Testing., , , and . European Test Symposium, page 123-130. IEEE Computer Society, (2006)PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits., , , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 306-315. Springer, (2000)X-masking during logic BIST and its impact on defect coverage., , , , , , , and . IEEE Trans. VLSI Syst., 14 (2): 193-202 (2006)Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults., , , , , and . MEMOCODE, page 181-187. IEEE Computer Society, (2007)Restrict Encoding for Mixed-Mode BIST., , , , , and . VTS, page 179-184. IEEE Computer Society, (2009)Implementing a Scheme for External Deterministic Self-Test., , , , and . VTS, page 101-106. IEEE Computer Society, (2005)A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips., , , , and . Asian Test Symposium, page 22-27. IEEE Computer Society, (2005)