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Deterministic Logic BIST for Transition Fault Testing.

V. Gherman, H. Wunderlich, J. Schlöffel, and M. Garbers. European Test Symposium, page 123-130. IEEE Computer Society, (2006)

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apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

Other publications of authors with the same name

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).R. Drechsler, S. Eggersglüß, G. Fey, J. Schlöffel, and D. Tille. it - Information Technology, 51 (2): 102-111 (2009)Cell-aware analysis for small-delay effects and production test results from different fault models.F. Hapke, J. Schlöffel, W. Redemund, A. Glowatz, J. Rajski, M. Reese, J. Rearick, and J. Rivers. ITC, page 1-8. IEEE Computer Society, (2011)Deterministic Logic BIST for Transition Fault Testing.V. Gherman, H. Wunderlich, J. Schlöffel, and M. Garbers. European Test Symposium, page 123-130. IEEE Computer Society, (2006)PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.J. Shi, G. Fey, R. Drechsler, A. Glowatz, F. Hapke, and J. Schlöffel. ISVLSI, page 212-217. IEEE Computer Society, (2005)X-masking during logic BIST and its impact on defect coverage.Y. Tang, H. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Schlöffel, F. Hapke, and M. Wittke. IEEE Trans. VLSI Syst., 14 (2): 193-202 (2006)PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits.A. Herrmann, E. Barke, M. Silvant, and J. Schlöffel. PATMOS, volume 1918 of Lecture Notes in Computer Science, page 306-315. Springer, (2000)Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.S. Eggersglüß, G. Fey, R. Drechsler, A. Glowatz, F. Hapke, and J. Schlöffel. MEMOCODE, page 181-187. IEEE Computer Society, (2007)Resistive Bridging Fault Simulation of Industrial Circuits.P. Engelke, I. Polian, J. Schlöffel, and B. Becker. DATE, page 628-633. ACM, (2008)Deterministic logic BIST for transition fault testing.V. Gherman, H. Wunderlich, J. Schlöffel, and M. Garbers. IET Computers & Digital Techniques, 1 (3): 180-186 (2007)Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model.A. Palit, V. Meyer, W. Anheier, and J. Schlöffel. DFT, page 174-182. IEEE Computer Society, (2004)

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Disambiguation of "Schlöffel, Jürgen"

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Deterministic Logic BIST for Transition Fault Testing.

Please choose a person to relate this publication to

apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Schlöffel, Jürgen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Deterministic Logic BIST for Transition Fault Testing.

Please choose a person to relate this publication to

apl. Prof. Dr. Jürgen Pleiss University of Stuttgart

Univ. -Prof. Dr. Jürgen Pafel University of Stuttgart

Dr. rer. nat. Jürgen Steinwandel University of Stuttgart

Hon. -Prof. Dr. Jürgen Hammer University of Stuttgart

Hon. -Prof. Dr. Jürgen Blum University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
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Deterministic Logic BIST for Transition Fault Testing.