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Disambiguation of "Chakrabarty, Krishnendu"

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SOC test planning using virtual test access architectures.

, , and . IEEE Trans. VLSI Syst., 12 (12): 1263-1276 (2004)

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Other publications of authors with the same name

Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.. DFT, IEEE Computer Society, (2006)A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks., and . IEEE Trans. Computers, 54 (8): 978-991 (2005)Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip., , and . IEEE Trans. Computers, 52 (12): 1619-1632 (2003)Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs., and . IEEE Trans. Computers, 63 (3): 691-702 (2014)An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications., , , and . J. Low Power Electronics, 10 (3): 506-518 (2014)Wafer-Level Modular Testing of Core-Based SoCs., and . IEEE Trans. VLSI Syst., 15 (10): 1144-1154 (2007)Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs., , , and . IEEE Trans. VLSI Syst., 17 (4): 587-592 (2009)Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics., , , and . IET Computers & Digital Techniques, 3 (6): 553-569 (2009)MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (11): 1762-1767 (2011)Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM., and . ASP-DAC, page 532-537. IEEE, (2015)