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Disambiguation of "Sehgal, Anuja"

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SOC test planning using virtual test access architectures.

, , and . IEEE Trans. VLSI Syst., 12 (12): 1263-1276 (2004)

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Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs., and . ICCAD, page 88-93. IEEE Computer Society, (2005)IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores., , , and . ITC, page 1203-1212. IEEE Computer Society, (2004)Test Data Volume Comparison: Monolithic vs. Modular SoC Testing., , , , and . IEEE Design & Test of Computers, 26 (3): 25-37 (2009)Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores., , , and . DATE, page 50-55. IEEE Computer Society, (2005)Test access mechanism for multiple identical cores., , , , and . ITC, page 1-10. IEEE Computer Society, (2009)Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs., and . IEEE Trans. Computers, 56 (1): 120-133 (2007)SOC test planning using virtual test access architectures., , and . IEEE Trans. VLSI Syst., 12 (12): 1263-1276 (2004)Power-aware SoC test planning for effective utilization of port-scalable testers., , and . ACM Trans. Design Autom. Electr. Syst., 13 (3): 53:1-53:19 (2008)Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores, , , and . CoRR, (2007)Test cost reduction for SOCs using virtual TAMs and lagrange multipliers., , , and . DAC, page 738-743. ACM, (2003)