%0 Journal Article %1 journals/tvlsi/SehgalIC04 %A Sehgal, Anuja %A Iyengar, Vikram %A Chakrabarty, Krishnendu %D 2004 %J IEEE Trans. VLSI Syst. %K dblp %N 12 %P 1263-1276 %T SOC test planning using virtual test access architectures. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#SehgalIC04 %V 12

@article{journals/tvlsi/SehgalIC04, added-at = {2016-03-15T00:00:00.000+0100}, author = {Sehgal, Anuja and Iyengar, Vikram and Chakrabarty, Krishnendu}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/286966a6709383336052d076e6be0c6fd/dblp}, ee = {http://dx.doi.org/10.1109/TVLSI.2004.834228}, interhash = {07ed04534717ffb74e897b187402ede2}, intrahash = {86966a6709383336052d076e6be0c6fd}, journal = {IEEE Trans. VLSI Syst.}, keywords = {dblp}, number = 12, pages = {1263-1276}, timestamp = {2016-03-16T10:32:01.000+0100}, title = {SOC test planning using virtual test access architectures.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#SehgalIC04}, volume = 12, year = 2004 }