%0 Journal Article %1 journals/tc/IyengarCM03 %A Iyengar, Vikram %A Chakrabarty, Krishnendu %A Marinissen, Erik Jan %D 2003 %J IEEE Trans. Computers %K dblp %N 12 %P 1619-1632 %T Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip. %U http://dblp.uni-trier.de/db/journals/tc/tc52.html#IyengarCM03 %V 52

@article{journals/tc/IyengarCM03, added-at = {2015-12-22T00:00:00.000+0100}, author = {Iyengar, Vikram and Chakrabarty, Krishnendu and Marinissen, Erik Jan}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2d071b8a5b35516d24801ac173c60b5b2/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TC.2003.1252857}, interhash = {2a9ac2bd1fb380b8dce3b911ffd21952}, intrahash = {d071b8a5b35516d24801ac173c60b5b2}, journal = {IEEE Trans. Computers}, keywords = {dblp}, number = 12, pages = {1619-1632}, timestamp = {2016-02-02T02:36:59.000+0100}, title = {Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.}, url = {http://dblp.uni-trier.de/db/journals/tc/tc52.html#IyengarCM03}, volume = 52, year = 2003 }