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Disambiguation of "Chattopadhyay, Anupam"

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High-Performance Hardware Implementation for RC4 Stream Cipher.

, , , , and . IEEE Trans. Computers, 62 (4): 730-743 (2013)

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Other publications of authors with the same name

Trace Buffer Attack: Security versus observability study in post-silicon debug., , and . VLSI-SoC, page 355-360. IEEE, (2015)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)Power-efficient Instruction Encoding Optimization for Embedded Processors., , , and . VLSI Design, page 595-600. IEEE Computer Society, (2007)Designing stream ciphers with scalable data-widths: a case study with HC-128., and . J. Cryptographic Engineering, 4 (2): 135-143 (2014)Design space exploration of partially re-configurable embedded processors., , , , , , and . DATE, page 319-324. EDA Consortium, San Jose, CA, USA, (2007)Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation., , , and . ICCD, page 193-199. IEEE Computer Society, (2005)Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation., , , , and . ASAP, page 188-189. IEEE Computer Society, (2014)Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors., , , , , , and . IEEE International Workshop on Rapid System Prototyping, page 189-194. IEEE Computer Society, (2007)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distrib. Syst., 29 (8): 1707-1720 (2018)