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Disambiguation of "Merchant, Farhad"

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Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization.

, , , , , and . IEEE Trans. Parallel Distrib. Syst., 29 (8): 1707-1720 (2018)

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Other publications of authors with the same name

Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic., , , and . VLSI Design, page 415-420. IEEE Computer Society, (2016)A Fully Pipelined Modular Multiple Precision Floating Point Multiplier with Vector Support., , , and . ISED, page 45-50. IEEE Computer Society, (2011)A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms., , , , and . VLSI-DAT, page 1-4. IEEE, (2019)A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design., , , , , , and . VLSI Design, page 64-69. IEEE, (2019)Applying Modified Householder Transform to Kalman Filter., , , , , , and . VLSI Design, page 431-436. IEEE, (2019)Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation., , , , and . ASAP, page 188-189. IEEE Computer Society, (2014)Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distrib. Syst., 29 (8): 1707-1720 (2018)Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization., , , , , , and . CoRR, (2018)Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design., , , , , and . CoRR, (2016)