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The evolution of standard cell libraries for future technology nodes.

J. Walker, J. Hilder, D. Reid, A. Asenov, S. Roy, C. Millar, and A. Tyrrell. Genetic Programming and Evolvable Machines, 12 (3): 235-256 (2011)

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Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.A. Asenov, J. Ding, D. Reid, P. Asenov, S. Amoroso, F. Adamu-Lema, and L. Gerrer. ISCAS, page 2449-2452. IEEE, (2015)Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, C. Millar, S. Roy, Z. Liu, S. Furber, and A. Asenov. DATE, page 1537-1540. IEEE, (2011)Speed-Up of Scalable Iterative Linear Solvers Implemented on an Array of Transputers.A. Asenov, D. Reid, and J. Barker. Parallel Computing, 20 (3): 375-387 (1994)Statistical simulation of random dopant induced threshold voltage fluctuations for 35 nm channel length MOSFET.U. Kovac, D. Reid, C. Millar, G. Roy, S. Roy, and A. Asenov. Microelectronics Reliability, 48 (8-9): 1572-1575 (2008)Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.L. Gerrer, J. Ding, S. Amoroso, F. Adamu-Lema, R. Hussin, D. Reid, C. Millar, and A. Asenov. Microelectronics Reliability, 54 (4): 682-697 (2014)Investigation of SRAM using BTI-aware statistical compact models.J. Ding, D. Reid, C. Millar, and A. Asenov. ESSDERC, page 186-189. IEEE, (2013)The evolution of standard cell libraries for future technology nodes.J. Walker, J. Hilder, D. Reid, A. Asenov, S. Roy, C. Millar, and A. Tyrrell. Genetic Programming and Evolvable Machines, 12 (3): 235-256 (2011)Enabling Cutting-Edge Semiconductor Simulation through Grid Technology.A. Asenov, D. Reid, C. Millar, S. Roy, G. Roy, R. Sinnott, G. Stewart, and G. Stewart. LSSC, volume 5910 of Lecture Notes in Computer Science, page 369-378. Springer, (2009)Speed-Up of Scalable Iterative Linear Solvers Implemented on an Array of Transputers.A. Asenov, D. Reid, and J. Barker. Parallel Computing, 21 (4): 669-682 (1995)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.B. Cheng, X. Wang, A. Brown, J. Kuang, D. Reid, C. Millar, S. Nassif, and A. Asenov. ISCAS, page 2339-2342. IEEE, (2013)

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Disambiguation of "Reid, Dave"

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The evolution of standard cell libraries for future technology nodes.

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Disambiguation of "Reid, Dave"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML The evolution of standard cell libraries for future technology nodes.

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The evolution of standard cell libraries for future technology nodes.