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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.

L. Gerrer, J. Ding, S. Amoroso, F. Adamu-Lema, R. Hussin, D. Reid, C. Millar, and A. Asenov. Microelectronics Reliability, 54 (4): 682-697 (2014)

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SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.B. Cheng, X. Wang, A. Brown, J. Kuang, D. Reid, C. Millar, S. Nassif, and A. Asenov. ISCAS, page 2339-2342. IEEE, (2013)An advanced statistical compact model strategy for SRAM simulation at reduced VDD.P. Asenov, D. Reid, S. Roy, C. Millar, and A. Asenov. ESSDERC, page 205-208. IEEE, (2012)Circuit design perspectives for Ge FinFET at 10nm and beyond.S. Sinha, L. Shifren, V. Chandra, B. Cline, G. Yeric, R. Aitken, B. Cheng, A. Brown, C. Riddet, C. Alexandar and 2 other author(s). ISQED, page 57-60. IEEE, (2015)Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.P. Asenov, D. New, D. Reid, C. Millar, S. Roy, and A. Asenov. ICICDT, page 29-32. IEEE, (2013)Progress on carbon nanotube BEOL interconnects.B. Uhlig, J. Liang, J. Lee, R. Ramos, A. Dhavamani, N. Nagy, J. Dijon, H. Okuno, D. Kalita, V. Georgiev and 11 other author(s). DATE, page 937-942. IEEE, (2018)Secure, Performance-Oriented Data Management for nanoCMOS Electronics.R. Sinnott, C. Bayliss, C. Davenhall, B. Harbulot, M. Jones, C. Millar, G. Roy, S. Roy, G. Stewart, J. Watt and 1 other author(s). eScience, page 87-94. IEEE Computer Society, (2008)Integrating Security Solutions to Support nanoCMOS Electronics Research.R. Sinnott, C. Bayliss, T. Doherty, D. Martin, C. Millar, G. Stewart, J. Watt, A. Asenov, G. Roy, S. Roy and 3 other author(s). ISPA, page 71-79. IEEE Computer Society, (2008)Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.M. Merrett, P. Asenov, Y. Wang, M. Zwolinski, D. Reid, C. Millar, S. Roy, Z. Liu, S. Furber, and A. Asenov. DATE, page 1537-1540. IEEE, (2011)Capturing intrinsic parameter fluctuations using the PSP compact model.B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy, and A. Asenov. DATE, page 650-653. IEEE, (2010)Modeling and simulation of transistor and circuit variability and reliability.A. Asenov, B. Cheng, D. Dideban, U. Kovac, N. Moezi, C. Millar, G. Roy, A. Brown, and S. Roy. CICC, page 1-8. IEEE, (2010)

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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.

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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.