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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.

, , , , , , , and . Microelectronics Reliability, 54 (4): 682-697 (2014)

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Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review., , , , , , , and . Microelectronics Reliability, 54 (4): 682-697 (2014)TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies., , , , , , , and . FET, volume 7 of Procedia Computer Science, page 148-149. Elsevier, (2011)Nanowire transistor solutions for 5nm and beyond., , , , , , and . ISQED, page 269-274. IEEE, (2016)Analysis of FinFET technology on memories., , , , , , , , and . IOLTS, page 169. IEEE Computer Society, (2012)Comparison of Si < 100 > and < 110 > crystal orientation nanowire transistor reliability using Poisson-Schrödinger and classical simulations., , , , and . Microelectronics Reliability, 55 (9-10): 1307-1312 (2015)A Virtual IC Factory in an Undergraduate Semiconductor Device Fabrication Laboratory., and . EUROSIM, page 1311-1316. Elsevier, (1995)Progress on carbon nanotube BEOL interconnects., , , , , , , , , and 11 other author(s). DATE, page 937-942. IEEE, (2018)Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits., , , , , , and . ISCAS, page 2449-2452. IEEE, (2015)New reliability mechanisms in memory design for sub-22nm technologies., , , , , , , , , and 7 other author(s). IOLTS, page 111-114. IEEE Computer Society, (2011)