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Disambiguation of "Bhardwaj, Sarvesh"

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The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis.

, , , , , and . IEEE Trans. VLSI Syst., 18 (2): 173-183 (2010)

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Other publications of authors with the same name

AU: Timing Analysis Under Uncertainty., , and . ICCAD, page 615-620. IEEE Computer Society / ACM, (2003)The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis., , , , , and . IEEE Trans. VLSI Syst., 18 (2): 173-183 (2010)Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs., and . ICCAD, page 713-718. IEEE Computer Society, (2005)A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (10): 1812-1825 (2008)Power Reduction of Functional Units Considering Temperature and Process Variations., , , and . VLSI Design, page 533-539. IEEE Computer Society, (2008)Temperature and Process Variations Aware Power Gating of Functional Units., , , , and . VLSI Design, page 515-520. IEEE Computer Society, (2008)Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic., , and . VLSI Design, page 240-. IEEE Computer Society, (2004)Secure and Robust Localization in a Wireless Ad Hoc Environment., , and . IEEE Trans. Vehicular Technology, 58 (3): 1480-1489 (2009)Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection., , and . J. Low Power Electronics, 2 (2): 240-250 (2006)An efficient combinationality check technique for the synthesis of cyclic combinational circuits., , , , and . ASP-DAC, page 212-215. ACM Press, (2005)