%0 Journal Article %1 journals/jolpe/BhardwajCV06 %A Bhardwaj, Sarvesh %A Cao, Yu %A Vrudhula, Sarma B. K. %D 2006 %J J. Low Power Electronics %K dblp %N 2 %P 240-250 %T Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. %U http://dblp.uni-trier.de/db/journals/jolpe/jolpe2.html#BhardwajCV06 %V 2

@article{journals/jolpe/BhardwajCV06, added-at = {2018-08-27T00:00:00.000+0200}, author = {Bhardwaj, Sarvesh and Cao, Yu and Vrudhula, Sarma B. K.}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/2650ee3a77beeee0532bda580f74cfc98/dblp}, ee = {https://doi.org/10.1166/jolpe.2006.065}, interhash = {7f8ec46ce05226bae398fd317bcbcd59}, intrahash = {650ee3a77beeee0532bda580f74cfc98}, journal = {J. Low Power Electronics}, keywords = {dblp}, number = 2, pages = {240-250}, timestamp = {2019-09-27T10:38:34.000+0200}, title = {Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection.}, url = {http://dblp.uni-trier.de/db/journals/jolpe/jolpe2.html#BhardwajCV06}, volume = 2, year = 2006 }