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Power Reduction of Functional Units Considering Temperature and Process Variations.

, , , and . VLSI Design, page 533-539. IEEE Computer Society, (2008)

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Temperature and Process Variations Aware Power Gating of Functional Units., , , , and . VLSI Design, page 515-520. IEEE Computer Society, (2008)Power Reduction of Functional Units Considering Temperature and Process Variations., , , and . VLSI Design, page 533-539. IEEE Computer Society, (2008)Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series., and . DSD, page 139-143. IEEE Computer Society, (2005)Fast and robust differential flipflops and their extension to multi-input threshold gates., , , and . ISCAS, page 822-825. IEEE, (2015)Identification of Threshold Functions and Synthesis of Threshold Networks., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (5): 665-677 (2011)Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (12): 2820-2832 (2006)A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (10): 1812-1825 (2008)Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs., and . ICCAD, page 713-718. IEEE Computer Society, (2005)A fast, energy efficient, field programmable threshold-logic array., , and . FPT, page 300-305. IEEE, (2014)Statistical library characterization using arbitrary polynomial chaos., , and . LASCAS, page 1-4. IEEE, (2017)