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CHERI: a RISC capability machine for practical memory safety.. University of Cambridge, UK, (2014)British Library, EThOS.CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment., , , , , , , , , and 11 other author(s). ASPLOS, page 379-393. ACM, (2019)CHERI JNI: Sinking the Java Security Model into the C., , , , , , , , , and 5 other author(s). ASPLOS, page 569-583. ACM, (2017)Lane Change and Merge Maneuvers for Connected and Automated Vehicles: A Survey., , , , , , , , , and 2 other author(s). IEEE Trans. Intelligent Vehicles, 1 (1): 105-120 (2016)Beyond the PDP-11: Architectural Support for a Memory-Safe C Abstract Machine., , , , , , , , and . ASPLOS, page 117-130. ACM, (2015)CheriRTOS: A Capability Model for Embedded Devices., , , , , , , , , and 6 other author(s). ICCD, page 92-99. IEEE Computer Society, (2018)A 64-bit MIPS processor running freebsd on a portable FPGA tablet., , and . FPL, page 1. IEEE, (2013)Fast Protection-Domain Crossing in the CHERI Capability-System Architecture., , , , , , , , , and 9 other author(s). IEEE Micro, 36 (5): 38-49 (2016)CHERI Concentrate: Practical Compressed Capabilities., , , , , , , , , and 4 other author(s). IEEE Trans. Computers, 68 (10): 1455-1469 (2019)The CHERI capability model: Revisiting RISC in an age of risk., , , , , , , , , and . ISCA, page 457-468. IEEE Computer Society, (2014)