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Disambiguation of "Moore, Simon W."

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The CHERI capability model: Revisiting RISC in an age of risk.

, , , , , , , , , and . ISCA, page 457-468. IEEE Computer Society, (2014)

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Hon. -Prof. Dr. -Ing. Volker Simon University of Stuttgart

Univ. -Prof. Dr. -Ing. Sven Simon University of Stuttgart

Adina Lucia Simonovic University of Stuttgart

Kai Simon University of Stuttgart

Sara Simonovska University of Stuttgart

 

Other publications of authors with the same name

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems., , , , and . ICCD, page 73-78. IEEE Computer Society, (2000)Exploring hard and soft networks-on-chip for FPGAs., and . FPT, page 261-264. IEEE, (2008)Point to Point GALS Interconnect., , , and . ASYNC, page 69-75. IEEE Computer Society, (2002)Rapid codesign of a soft vector processor and its compiler., and . FPL, page 1-4. IEEE, (2014)A spiking neural network on a portable FPGA tablet., , , and . FPL, page 1. IEEE, (2013)A Vector Approach to Cryptography Implementation., and . DRMTICS, volume 3919 of Lecture Notes in Computer Science, page 277-297. Springer, (2005)Reliably prototyping large SoCs using FPGA clusters., , and . ReCoSoC, page 1-8. IEEE, (2014)A Power and Energy Exploration of Network-on-Chip Architectures., , and . NOCS, page 163-172. IEEE Computer Society, (2007)Through computer architecture, darkly., , , , and . Commun. ACM, 62 (6): 25-27 (2019)Security Evaluation of Asynchronous Circuits., , , , and . CHES, volume 2779 of Lecture Notes in Computer Science, page 137-151. Springer, (2003)