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Point to Point GALS Interconnect., , , and . ASYNC, page 69-75. IEEE Computer Society, (2002)Rapid codesign of a soft vector processor and its compiler., and . FPL, page 1-4. IEEE, (2014)Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems., , , , and . ICCD, page 73-78. IEEE Computer Society, (2000)Exploring hard and soft networks-on-chip for FPGAs., and . FPT, page 261-264. IEEE, (2008)A spiking neural network on a portable FPGA tablet., , , and . FPL, page 1. IEEE, (2013)Reliably prototyping large SoCs using FPGA clusters., , and . ReCoSoC, page 1-8. IEEE, (2014)A Power and Energy Exploration of Network-on-Chip Architectures., , and . NOCS, page 163-172. IEEE Computer Society, (2007)Through computer architecture, darkly., , , , and . Commun. ACM, 62 (6): 25-27 (2019)CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization., , , , , , , , , and 5 other author(s). IEEE Symposium on Security and Privacy, page 20-37. IEEE Computer Society, (2015)Efficient Tagged Memory., , , , , , , , , and 8 other author(s). ICCD, page 641-648. IEEE Computer Society, (2017)