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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

D. Moss, K. Srivatsan, E. Nurvitadhi, P. Ratuszniak, C. Johnson, J. Sim, A. Mishra, D. Marr, S. Subhaschandra, and P. Leong. FPGA, page 107-116. ACM, (2018)

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Hon. -Prof. Dr. -Ing. Volker Simon University of Stuttgart

Carl Simon University of Stuttgart

Jonas Simolka University of Stuttgart

Dr. rer. nat. Ekin Simsek Sanli University of Stuttgart

Univ. -Prof. Dr. -Ing. Sven Simon University of Stuttgart

Other publications of authors with the same name

CoolPIM: Thermal-Aware Source Throttling for Efficient PIM Instruction Offloading.L. Nai, R. Hadidi, H. Xiao, H. Kim, J. Sim, and H. Kim. IPDPS, page 680-689. IEEE Computer Society, (2018)Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.E. Nurvitadhi, J. Sim, D. Sheffield, A. Mishra, S. Krishnan, and D. Marr. FPL, page 1-4. IEEE, (2016)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch.J. Sim, G. Loh, H. Kim, M. O'Connor, and M. Thottethodi. MICRO, page 247-257. IEEE Computer Society, (2012)Specializing FGPU for Persistent Deep Learning.R. Ma, D. Chiou, J. Hsu, T. Tan, E. Nurvitadhi, D. Sheffield, R. Pelt, M. Langhammer, J. Sim, and A. Dasu. FPL, page 326-333. IEEE, (2019)A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches.J. Sim, G. Loh, V. Sridharan, and M. O'Connor. IEEE Micro, 34 (3): 80-90 (2014)FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion.J. Sim, J. Lee, M. Qureshi, and H. Kim. ISCA, page 321-332. IEEE Computer Society, (2012)Resilient die-stacked DRAM caches.J. Sim, G. Loh, V. Sridharan, and M. O'Connor. ISCA, page 416-427. ACM, (2013)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FPGA, page 119. ACM, (2019)BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models.J. Lee, J. Sim, and H. Kim. PACT, page 241-252. IEEE Computer Society, (2015)Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FCCM, page 199-207. IEEE, (2019)

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Disambiguation of "Sim, Jaewoong"

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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

Please choose a person to relate this publication to

Hon. -Prof. Dr. -Ing. Volker Simon University of Stuttgart

Carl Simon University of Stuttgart

Jonas Simolka University of Stuttgart

Dr. rer. nat. Ekin Simsek Sanli University of Stuttgart

Univ. -Prof. Dr. -Ing. Sven Simon University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Sim, Jaewoong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

Please choose a person to relate this publication to

Hon. -Prof. Dr. -Ing. Volker Simon University of Stuttgart

Carl Simon University of Stuttgart

Jonas Simolka University of Stuttgart

Dr. rer. nat. Ekin Simsek Sanli University of Stuttgart

Univ. -Prof. Dr. -Ing. Sven Simon University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.