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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

D. Moss, K. Srivatsan, E. Nurvitadhi, P. Ratuszniak, C. Johnson, J. Sim, A. Mishra, D. Marr, S. Subhaschandra, and P. Leong. FPGA, page 107-116. ACM, (2018)

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Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy.A. Mishra, and D. Marr. CoRR, (2017)Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.E. Nurvitadhi, D. Kwon, A. Jafari, A. Boutros, J. Sim, P. Tomson, H. Sumbul, G. Chen, P. Knag, R. Kumar and 6 other author(s). FPGA, page 119. ACM, (2019)Apprentice: Using Knowledge Distillation Techniques To Improve Low-Precision Network Accuracy.A. Mishra, and D. Marr. ICLR (Poster), OpenReview.net, (2018)Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.E. Nurvitadhi, J. Sim, D. Sheffield, A. Mishra, S. Krishnan, and D. Marr. FPL, page 1-4. IEEE, (2016)Low Precision RNNs: Quantizing RNNs Without Losing Accuracy.S. Kapur, A. Mishra, and D. Marr. CoRR, (2017)Accelerating Deep Convolutional Networks using low-precision and sparsity.G. Venkatesh, E. Nurvitadhi, and D. Marr. CoRR, (2016)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)WRPN: Wide Reduced-Precision Networks.A. Mishra, E. Nurvitadhi, J. Cook, and D. Marr. CoRR, (2017)Hardware accelerator for analytics of sparse data.E. Nurvitadhi, A. Mishra, Y. Wang, G. Venkatesh, and D. Marr. DATE, page 1616-1621. IEEE, (2016)A sparse matrix vector multiply accelerator for support vector machine.E. Nurvitadhi, A. Mishra, and D. Marr. CASES, page 109-116. IEEE, (2015)

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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.