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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

D. Moss, K. Srivatsan, E. Nurvitadhi, P. Ratuszniak, C. Johnson, J. Sim, A. Mishra, D. Marr, S. Subhaschandra, and P. Leong. FPGA, page 107-116. ACM, (2018)

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Rishikeya Mishra University of Stuttgart

K. Stahl

K. Lindow

K. Gaiser

Grzegorz K. Karch

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Performance and power optimization through data compression in Network-on-Chip architectures.R. Das, A. Mishra, C. Nicopoulos, D. Park, V. Narayanan, R. Iyer, M. Yousif, and C. Das. HPCA, page 215-225. IEEE Computer Society, (2008)ScalCore: Designing a core for voltage scalability.B. Gopireddy, C. Song, J. Torrellas, N. Kim, A. Agrawal, and A. Mishra. HPCA, page 681-693. IEEE Computer Society, (2016)WRPN: Wide Reduced-Precision Networks.A. Mishra, E. Nurvitadhi, J. Cook, and D. Marr. CoRR, (2017)Application-aware prefetch prioritization in on-chip networks.N. Nachiappan, A. Mishra, M. Kandemir, A. Sivasubramaniam, O. Mutlu, and C. Das. PACT, page 441-442. ACM, (2012)In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.E. Nurvitadhi, J. Cook, A. Mishra, D. Marr, K. Nealis, P. Colangelo, A. Ling, D. Capalija, U. Aydonat, A. Dasu and 1 other author(s). FPL, page 106-110. IEEE Computer Society, (2018)Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs.P. Colangelo, N. Nasiri, E. Nurvitadhi, A. Mishra, M. Margala, and K. Nealis. FCCM, page 73-80. IEEE Computer Society, (2018)A case for integrated processor-cache partitioning in chip multiprocessors.S. Srikantaiah, R. Das, A. Mishra, C. Das, and M. Kandemir. SC, ACM, (2009)A heterogeneous multiple network-on-chip design: an application-aware approach.A. Mishra, O. Mutlu, and C. Das. DAC, page 36:1-36:10. ACM, (2013)Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC.E. Nurvitadhi, J. Sim, D. Sheffield, A. Mishra, S. Krishnan, and D. Marr. FPL, page 1-4. IEEE, (2016)Towards characterizing cloud backend workloads: insights from Google compute clusters.A. Mishra, J. Hellerstein, W. Cirne, and C. Das. SIGMETRICS Performance Evaluation Review, 37 (4): 34-41 (2010)

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Disambiguation of "Mishra, Asit K."

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A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

Please choose a person to relate this publication to

Rishikeya Mishra University of Stuttgart

K. Stahl

K. Lindow

K. Gaiser

Grzegorz K. Karch

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Mishra, Asit K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.

Please choose a person to relate this publication to

Rishikeya Mishra University of Stuttgart

K. Stahl

K. Lindow

K. Gaiser

Grzegorz K. Karch

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study.