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Disambiguation of "O'Connor, Mike"

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A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches.

, , , and . IEEE Micro, 34 (3): 80-90 (2014)

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Mike Söhner University of Stuttgart

Mike Kornely University of Stuttgart

Mike Kopp University of Stuttgart

Mike Holz University of Stuttgart

Mike Hartmann University of Stuttgart

 

Other publications of authors with the same name

Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms., , , , , , , , , and . POMACS, 1 (1): 10:1-10:42 (2017)What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study., , , , , , , , , and 2 other author(s). SIGMETRICS (Abstracts), page 110. ACM, (2018)Open Standard Content Cookies: Utility vs. Privacy., , , and . WebNet, AACE, (1997)Enabling Efficient Dynamic Resizing of Large DRAM Caches via A Hardware Consistent Hashing Mechanism., , , , , , , , and . CoRR, (2016)GPUDet: a deterministic GPU architecture., , , , and . ASPLOS, page 1-12. ACM, (2013)A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch., , , , and . MICRO, page 247-257. IEEE Computer Society, (2012)Performance analysis and validation of the picoJava processor., and . IEEE Micro, 19 (3): 66-72 (1999)Learning your limit: managing massively multithreaded caches through scheduling., , and . Commun. ACM, 57 (12): 91-98 (2014)Accelerated processing and the Fusion System Architecture.. ASP-DAC, page 93. IEEE, (2012)Network Communication as a Service-Oriented Capability., , , , , , , , and . High Performance Computing Workshop, volume 16 of Advances in Parallel Computing, page 96-127. IOS Press, (2006)