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Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)Long-Term Workload Phases: Duration Predictions and Applications to DVFS., , and . IEEE Micro, 25 (5): 39-51 (2005)Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities., , , , , , , and . MICRO, page 368-380. IEEE, (2014)Abstraction and microarchitecture scaling in early-stage power modeling., , , , and . HPCA, page 394-405. IEEE Computer Society, (2011)CPU Accounting for Multicore Processors., , , , , and . IEEE Trans. Computers, 61 (2): 251-264 (2012)Exploring power management in multi-core systems., , , , , , , , , and 1 other author(s). ASP-DAC, page 708-713. IEEE, (2008)3D stacking of high-performance processors., , , , , , , , and . HPCA, page 500-511. IEEE Computer Society, (2014)ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs., , , , , and . PACT, page 203-213. IEEE Computer Society, (2009)Very Low Voltage (VLV) Design., , , , , , , , , and 15 other author(s). ICCD, page 601-604. IEEE Computer Society, (2017)Characterizing Power and Temperature Behavior of POWER6-Based System., , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 228-241 (2011)