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ETISS-ML: A multi-level instruction set simulator with RTL-level fault injection support for the evaluation of cross-layer resiliency techniques., , , , , and . DATE, page 609-612. IEEE, (2018)Cross-Layer Resilience: Challenges, Insights, and the Road Ahead., , , , , , , , , and 3 other author(s). DAC, page 198. ACM, (2019)Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights., , , , , , , , , and 6 other author(s). ICCD, page 593-596. IEEE Computer Society, (2017)Causal commutative arrows., , and . J. Funct. Program., 21 (4-5): 467-496 (2011)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Project 38: Innovative Architectures for High-Performance Computing Systems.. IA3@SC, page 1. IEEE, (2021)Abstract factories and the shape calculator., , , and . OOPSLA Companion, page 101-102. ACM, (2004)Marine biology simulation., , , and . OOPSLA Companion, page 109-110. ACM, (2004)Very Low Voltage (VLV) Design., , , , , , , , , and 15 other author(s). ICCD, page 601-604. IEEE Computer Society, (2017)Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study., , , and . ITC, page 1-10. IEEE Computer Society, (2013)