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Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis., , , , , , and . ASP-DAC, page 218-225. IEEE, (2016)Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (6): 1056-1069 (2019)Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation., , , , , and . DAC, page 7:1-7:6. ACM, (2016)High-level Synthesis for Low-power Design., , , and . IPSJ Trans. System LSI Design Methodology, (2015)Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights., , , , , , , , , and 6 other author(s). ICCD, page 593-596. IEEE Computer Society, (2017)High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths., , , and . DAC, page 161:1-161:6. ACM, (2015)Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis., , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 38 (7): 1345-1358 (2019)Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles., , , and . DAC, page 53:1-53:6. ACM, (2015)