PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Szafaryn, Lukasz G."

Author of the publication

copydeleteadd this publication to your clipboard
Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights.

, , , , , , , , , , , , , , , and . ICCD, page 593-596. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Lukasz Brodecki University of Stuttgart

G. Daiß

G. Wagner

Dr. Guido Reina University of Stuttgart

Univ. -Prof. Dr. Thomas Graf University of Stuttgart

Synchrotron X-ray video of full-penetration laser welding of aluminum AA1050A, , , , , , and . Dataset, (2024)
 

Other publications of authors with the same name

The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Trellis: Portability across architectures with a high-level framework., , , and . J. Parallel Distrib. Comput., 73 (10): 1400-1413 (2013)Killi: Runtime Fault Classification to Deploy Low Voltage Caches without MBIST., , , , and . HPCA, page 304-316. IEEE, (2019)A characterization of the Rodinia benchmark suite with comparison to contemporary CMP workloads., , , , , and . IISWC, page 1-11. IEEE Computer Society, (2010)Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights., , , , , , , , , and 6 other author(s). ICCD, page 593-596. IEEE Computer Society, (2017)Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core., , and . IEEE Micro, 33 (4): 56-65 (2013)Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)., , , , , , , , , and 1 other author(s). IEEE Trans. on CAD of Integrated Circuits and Systems, 37 (9): 1839-1852 (2018)Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)., , , , , , , , , and 1 other author(s). CoRR, (2017)Clear: c̲ross-l̲ayer e̲xploration for a̲rchitecting r̲esilience combining hardware and software techniques to tolerate soft errors in processor cores., , , , , , , , , and 1 other author(s). DAC, page 68:1-68:6. ACM, (2016)