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Characterizing Power and Temperature Behavior of POWER6-Based System.

, , , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (3): 228-241 (2011)

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Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)Static Locality Analysis for Cache Management., , and . IEEE PACT, page 261-271. IEEE Computer Society, (1997)Access to streams in multiprocessor systems., , and . PDP, page 310-316. IEEE, (1993)A latency-conscious SMT branch prediction architecture., , , and . IJHPCN, 2 (1): 11-21 (2004)Decoupled Vector Architectures., and . HPCA, page 281-290. IEEE Computer Society, (1996)Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Errata on "Measuring Experimental Error in Microprocessor Simulation"., , , , , , and . SIGARCH Computer Architecture News, 30 (1): 2-4 (2002)Virtual registers., , , and . HiPC, page 364-369. IEEE Computer Society, (1997)Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications., , , , and . SAMOS, volume 5114 of Lecture Notes in Computer Science, page 53-64. Springer, (2008)Exploiting instruction- and data-level parallelism., and . IEEE Micro, 17 (5): 20-27 (1997)