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Gate movement for timing improvement on row based Dual-VDD designs.

H. Xiang, L. Reddy, H. Qian, C. Zhou, Y. Lin, F. Yee, A. Sullivan, and P. Lu. ISQED, page 423-429. IEEE, (2016)

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Xiao Fei University of Stuttgart

Hao Lu University of Stuttgart

Yong Lu University of Stuttgart

Carolin Feifel University of Stuttgart

Mathias Feinler University of Stuttgart

Other publications of authors with the same name

A Semi-Custom Design Flow in High-Performance Microprocessor Design.G. Northrop, and P. Lu. DAC, page 426-431. ACM, (2001)A pulsed low-voltage swing latch for reduced power dissipation in high-frequency microprocessors.P. Lu, N. Cao, L. Sigal, P. Woltgens, R. Robertazzi, and D. Heidel. ISLPED, page 85-88. ACM, (2006)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology.T. Kim, P. Lu, K. Jenkins, and C. Kim. IEEE Trans. VLSI Syst., 23 (7): 1360-1364 (2015)Design of ring oscillator structures for measuring isolated NBTI and PBTI.T. Kim, P. Lu, and C. Kim. ISCAS, page 1580-1583. IEEE, (2012)Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology.P. Lu, K. Jenkins, K. Muller, and R. Schaufler. IRPS, page 6. IEEE, (2015)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)Gate movement for timing improvement on row based Dual-VDD designs.H. Xiang, L. Reddy, H. Qian, C. Zhou, Y. Lin, F. Yee, A. Sullivan, and P. Lu. ISQED, page 423-429. IEEE, (2016)SOI for digital CMOS VLSI: design considerations and advances.C. Chuang, P. Lu, and C. Anderson. Proc. IEEE, 86 (4): 689-720 (1998)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)

PUMA

Disambiguation of "Lu, Pong-Fei"

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Gate movement for timing improvement on row based Dual-VDD designs.

Please choose a person to relate this publication to

Xiao Fei University of Stuttgart

Hao Lu University of Stuttgart

Yong Lu University of Stuttgart

Carolin Feifel University of Stuttgart

Mathias Feinler University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Lu, Pong-Fei"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Gate movement for timing improvement on row based Dual-VDD designs.

Please choose a person to relate this publication to

Xiao Fei University of Stuttgart

Hao Lu University of Stuttgart

Yong Lu University of Stuttgart

Carolin Feifel University of Stuttgart

Mathias Feinler University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Gate movement for timing improvement on row based Dual-VDD designs.