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Gate movement for timing improvement on row based Dual-VDD designs.

H. Xiang, L. Reddy, H. Qian, C. Zhou, Y. Lin, F. Yee, A. Sullivan, and P. Lu. ISQED, page 423-429. IEEE, (2016)

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Dr. -Ing. Huan Zhou University of Stuttgart

Qian Zhou University of Stuttgart

Yangchao Zhou University of Stuttgart

Other publications of authors with the same name

Gate movement for timing improvement on row based Dual-VDD designs.H. Xiang, L. Reddy, H. Qian, C. Zhou, Y. Lin, F. Yee, A. Sullivan, and P. Lu. ISQED, page 423-429. IEEE, (2016)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)64-bit prefix adders: Power-efficient topologies and design solutions.C. Zhou, B. Fleischer, M. Gschwind, and R. Puri. CICC, page 179-182. IEEE, (2009)Synthesis design strategies for energy-efficient microprocessors.C. Zhou, Y. Lin, P. Lu, B. Fleischer, D. Frank, and L. Chang. ICCD, page 103-108. IEEE Computer Society, (2016)A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.S. Lee, A. Agrawal, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). IEEE J. Solid State Circuits, 57 (1): 182-197 (2022)Row Based Dual-VDD Island Generation and Placement.H. Xiang, H. Qian, C. Zhou, Y. Lin, F. Yee, A. Sullivan, and P. Lu. DAC, page 125:1-125:6. ACM, (2014)Efficient AI System Design With Cross-Layer Approximate Computing.S. Venkataramani, X. Sun, N. Wang, C. Chen, J. Choi, M. Kang, A. Agarwal, J. Oh, S. Jain, T. Babinsky and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)

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Disambiguation of "Zhou, Ching"

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Gate movement for timing improvement on row based Dual-VDD designs.

Please choose a person to relate this publication to

Dr. -Ing. Huan Zhou University of Stuttgart

Qian Zhou University of Stuttgart

Yangchao Zhou University of Stuttgart

Other publications of authors with the same name

Disambiguation

PUMA

Disambiguation of "Zhou, Ching"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Gate movement for timing improvement on row based Dual-VDD designs.

Please choose a person to relate this publication to

Dr. -Ing. Huan Zhou University of Stuttgart

Qian Zhou University of Stuttgart

Yangchao Zhou University of Stuttgart

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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Gate movement for timing improvement on row based Dual-VDD designs.