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Disambiguation of "Yoshikawa, Takefumi"

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A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment.

, , , , and . J. Electron. Test., 37 (5): 675-684 (2021)

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Other publications of authors with the same name

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics., , , , , and . IEEE Trans. VLSI Syst., 16 (9): 1187-1198 (2008)A Spread Spectrum Clock Generator Using Digital Tracking Scheme., , , and . IEICE Transactions, 88-C (6): 1288-1289 (2005)Timing margin enhancement technique for current mode interface., and . IEICE Electronic Express, 11 (19): 20140766 (2014)Design of self-biased fully differential receiver and crosstalk cancellation for capacitive coupled vertical interconnects in 3DICs., , , and . ISCAS, page 966-969. IEEE, (2013)A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 44 (3): 763-774 (2009)Design of Simultaneous Bi-Directional Transceivers Utilizing Capacitive Coupling for 3DICs in Face-to-Face Configuration., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (2): 257-265 (2012)A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs., , , and . IEEE Trans. on Circuits and Systems, 61-II (9): 706-710 (2014)An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration., , , , , , and . J. Solid-State Circuits, 46 (4): 986-991 (2011)Design of capacitive-coupling-based simultaneously bi-directional transceivers for 3DIC., , , and . 3DIC, page 1-4. IEEE, (2011)A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs., , , , , , , , and . IEICE Electronic Express, 11 (22): 20140949 (2014)