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Disambiguation of "Yamauchi, Hiroyuki"

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An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.

, , , , , and . IEEE Trans. VLSI Syst., 16 (9): 1187-1198 (2008)

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Other publications of authors with the same name

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies.. IEEE Trans. VLSI Syst., 18 (5): 763-774 (2010)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . J. Solid-State Circuits, 48 (3): 864-877 (2013)Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs., and . SoCC, page 318-323. IEEE, (2014)0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier., , , , , and . IEICE Transactions, 88-C (4): 630-638 (2005)Multi-Layer Logic - A Predicate Logic Including Data Structure as Knowledge Representation Language., and . New Generation Comput., 3 (4): 403-439 (1985)17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme., , , , , and . ISSCC, page 1-3. IEEE, (2015)A discussion on SRAM forward/inverse problem analyses for RTN long-tail distributions., , and . ISVLSI, page 58-63. IEEE Computer Socity, (2013)A filter design for blind deconvolution to decouple unknown RDF/RTN factors from complexly coupled SRAM margin variations., and . LASCAS, page 247-250. IEEE, (2016)A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V$_TH$ Read-Port, and Offset Cell VDD Biasing Techniques., , , , , , , , , and 1 other author(s). J. Solid-State Circuits, 48 (10): 2558-2569 (2013)A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme., , , , , , , , , and . J. Solid-State Circuits, 46 (4): 815-827 (2011)