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Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures

, , , , , and . IEEE transactions on computers, 66 (6): 957-970 (2017)
DOI: 10.1109/TC.2016.2616405

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Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms., , , and . EDCC, volume 1667 of Lecture Notes in Computer Science, page 339-350. Springer, (1999)Bit-flipping BIST., and . ICCAD, page 337-343. IEEE Computer Society / ACM, (1996)System reliability evaluation using concurrent multi-level simulation of structural faults., , , , , , , and . ITC, page 817. IEEE Computer Society, (2010)Tools and devices supporting the pseudo-exhaustive test., and . EURO-DAC, page 13-17. IEEE Computer Society, (1990)Generating pattern sequences for the pseudo-exhaustive test of MOS-circuits., and . FTCS, page 36-41. IEEE Computer Society, (1988)Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead., , and . European Test Symposium, page 53-58. IEEE Computer Society, (2009)Towards Variation-Aware Test Methods., , , , and . European Test Symposium, page 219-225. IEEE Computer Society, (2011)An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy., , and . European Test Symposium, page 91-96. IEEE Computer Society, (2007)Variation-aware deterministic ATPG., , , , , , , and . ETS, page 1-6. IEEE, (2014)Adapting an SoC to ATE Concurrent Test Capabilities., , , and . ITC, page 1169-1175. IEEE Computer Society, (2002)