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A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits.

, , , , , and . IEEE Trans. VLSI Syst., 15 (9): 1051-1054 (2007)

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Predicting the Performance of a 3D Processor-Memory Chip Stack., , , , , and . IEEE Design & Test of Computers, 22 (6): 540-547 (2005)A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme., , , , , , , , and . FPGA, page 248. ACM, (2003)The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA., , , , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-144. ACM, (2004)52 Gb/s 16: 1 transmitter in 0.13 μm SiGe BiCMOS technology., , , , and . IET Circuits, Devices & Systems, 1 (6): 427-432 (2007)Carry Chains for Ultra High-Speed SiGe HBT Adders., , , , , , and . IEEE Trans. on Circuits and Systems, 58-I (9): 2201-2210 (2011)Design of BiCMOS SRAMs for high-speed SiGe applications., , , , , , , , and . IET Circuits, Devices & Systems, 8 (6): 487-498 (2014)Reconfigurable 40 GHz BiCMOS uniform delay crossbar switch for broadband and wide tuning range narrowband applications., , , , , and . IET Circuits, Devices & Systems, 5 (3): 159-169 (2011)Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs., , , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 59-69. Springer, (2001)A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration., , , , , and . IEEE Trans. VLSI Syst., 18 (6): 967-977 (2010)A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block., , , , , , , and . Microprocessors and Microsystems, 29 (2-3): 121-131 (2005)