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Implementing End-to-End Register Data-Flow Continuous Self-Test., , , , and . IEEE Trans. Computers, 60 (8): 1194-1206 (2011)Control-Flow Recovery Validation Using Microarchitectural Invariants., , , and . DFT, page 209-216. IEEE Computer Society, (2011)Bus designs for time-probabilistic multicore processors., , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Low-cost checkpointing in automotive safety-relevant systems., and . DATE, page 91-96. ACM, (2015)A detailed methodology to compute Soft Error Rates in advanced technologies., , , and . DATE, page 217-222. IEEE, (2016)Evaluation of a Policy-Based QoS Management Architecture over an IPv6 DiffServ testbed., , , , and . TRIDENTCOM, page 1-9. IEEE, (2007)Online error detection and correction of erratic bits in register files., , , , and . IOLTS, page 81-86. IEEE Computer Society, (2009)On-Line Failure Detection and Confinement in Caches., , , , and . IOLTS, page 3-9. IEEE Computer Society, (2008)Power-Aware Adaptive Issue Queue and Register File., and . HiPC, volume 2913 of Lecture Notes in Computer Science, page 34-43. Springer, (2003)HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems., , , and . ECRTS, volume 106 of LIPIcs, page 3:1-3:22. Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, (2018)