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Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)A methodology for the characterization of process variation in NoC links., , and . DATE, page 685-690. IEEE, (2010)Design and integration of hierarchical-placement multi-level caches for real-time systems., , , and . DATE, page 455-460. IEEE, (2018)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems., , , , and . RTAS, page 267-278. IEEE Computer Society, (2016)Enabling High-Performance Crossbars through a Floorplan-Aware Design., , , , and . ICPP, page 269-278. IEEE Computer Society, (2012)Locality-aware cache random replacement policies., , , and . Journal of Systems Architecture - Embedded Systems Design, (2019)A new mechanism to deal with process variability in NoC links., , , and . IPDPS, page 1-11. IEEE, (2009)Design and implementation of a fair credit-based bandwidth sharing scheme for buses., , , and . DATE, page 926-929. IEEE, (2017)Probabilistic timing analysis on time-randomized platforms for the space domain., , , , , , , , , and 1 other author(s). DATE, page 738-739. IEEE, (2017)