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Locality-aware cache random replacement policies.

, , , and . Journal of Systems Architecture - Embedded Systems Design, (2019)

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Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors., , , , , , and . ISORC, page 208-217. IEEE Computer Society, (2015)Multicore Resource Management., , , , , and . IEEE Micro, 28 (3): 6-16 (2008)QoS for High-Performance SMT Processors in Embedded Systems., , , , , and . IEEE Micro, 24 (4): 24-31 (2004)SMT Malleability in IBM POWER5 and POWER6 Processors., , , , , , , and . IEEE Trans. Computers, 62 (4): 813-826 (2013)DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems., , , , and . ACM Trans. Design Autom. Electr. Syst., 22 (1): 16:1-16:26 (2016)Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation., , , and . ACM Trans. Design Autom. Electr. Syst., 20 (1): 10:1-10:25 (2014)Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns., , and . ISORC, page 142-149. IEEE Computer Society, (2016)Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)Locality-aware cache random replacement policies., , , and . Journal of Systems Architecture - Embedded Systems Design, (2019)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)