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Disambiguation of "Marinissen, Erik Jan"

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A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards.

, , , , , and . ITC-Asia, page 144-149. IEEE, (2017)

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Erik Eppinger University of Stuttgart

Tim Janz University of Stuttgart

Benedikt Janny

Erik Hesselmeier-Hüttmann University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

 

Other publications of authors with the same name

Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip., , and . IEEE Trans. Computers, 52 (12): 1619-1632 (2003)Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption., , , and . IEEE Trans. Computers, 64 (12): 3335-3347 (2015)Creating options for 3D-SIC testing.. DDECS, page 7. IEEE Computer Society, (2013)Efficient Wrapper/TAM Co-Optimization for Large SOCs., , and . DATE, page 491-498. IEEE Computer Society, (2002)Contactless testing: Possibility or pipe-dream?, , , , , , and . DATE, page 676-681. IEEE, (2009)Wrapper design for embedded core test., , , and . ITC, page 911-920. IEEE Computer Society, (2000)User-constrained test architecture design for modular SOC testing., , , , and . European Test Symposium, page 80-85. IEEE Computer Society, (2004)Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base., , , and . Asian Test Symposium, page 451-456. IEEE Computer Society, (2011)Test Cost Analysis for 3D Die-to-Wafer Stacking., , , and . Asian Test Symposium, page 435-441. IEEE Computer Society, (2010)Impact of 3D design choices on manufacturing cost., , , , and . 3DIC, page 1-5. IEEE, (2009)